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low jitter clock generator with eight lvpecl outputs data sheet ad9525 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is a ssumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features integrated ultra low noise synthesizer 8 differential 3. 6 ghz l vpecl outputs and 1 lvpecl sync output or 2 cmos sync outputs 2 differential reference inputs and 1 single - ended reference input applications lte and multicarrier gsm base stations cloc king high speed adcs, dacs ate and high performance instrumentation 40/100 gb/s ec otn line side c locking cable/docsis cmts c locking test and m easurement functional block dia gram refb pll dividers s spi control ad9525 refa refa refb sync_out sync_out refc clkin clkin out7 out7 out6 out6 out5 out5 out4 out4 out3 out3 out2 out2 out1 out1 out0 out0 100 1 1-001 figure 1. general description the ad9525 is de sig ned to support converter clock requirements for long - term evolution (lte) and multicarrier gsm base station designs. the ad9525 provides a low power, multi output, clock distribution function with low jitter performance, along with an on - chip pll that can be used with an external vco or vcxo . the vco input and eight lvpecl outputs can operate up to a frequency of 3.6 ghz. all outputs share a common divider tha t can p rovide a division of 1 to 6. the ad9525 offers a dedicated output that can be used to provide a programmable signal for reset ting or synchronizing a data converter. the output signal is activated by a spi write . the ad9525 is available in a 48- lead lfcsp and can be operated from a single 3.3 v supply. the external vcxo or vco can have an operating voltage of up to 5.5 v. the ad9525 operates over the extended industrial temperature range of ? 40c to +85c.
ad9525 data sheet rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 conditions ..................................................................................... 3 supply current .............................................................................. 3 power dissipation ......................................................................... 3 refa and refb input characteristics ...................................... 4 refc input character istics ........................................................ 4 clock inputs .................................................................................. 5 pll characteristics ...................................................................... 5 pll digital lock d etect .............................................................. 6 clock outputs ............................................................................... 6 timing characteristics ................................................................ 7 clock output ab solute time jitter (clock generation using external 122.88 mhz vcxo) .......................................... 8 clock output absolute time jitter (clock generation using external 1475 mhz vco) ............................................... 8 clock output absolute time jitter (clock generation using external 2.05 ghz vco) ................................................. 9 clock output absolute time jitter (clock generation using external 3 ghz vco) ...................................................... 9 clock output additive phase noise (distribution only; clock input to distribution output, including vco divider) .......................................................................................... 9 pd , reset , and ref_sel pins ................................................ 10 status and ref_mon pins .................................................. 10 serial control port ..................................................................... 11 absolute maximum ratings ......................................................... 12 thermal resistance .................................................................... 12 esd caution ................................................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 15 terminology .................................................................................... 18 detailed block diagram ................................................................ 19 theory of operation ...................................................................... 20 configuration of the pll .......................................................... 20 clock distribution ..................................................................... 23 sync_out ................................................................................ 23 r eset modes ................................................................................ 25 power - down modes .................................................................. 26 serial control port ......................................................................... 27 pin des criptions ......................................................................... 27 general operation of serial control port ............................... 27 the instruction word (16 bits) ................................................ 28 msb/lsb first transfers ........................................................... 28 control registers ............................................................................ 31 control register map overview .............................................. 31 register map descriptions ............................................................ 33 applications information .............................................................. 45 frequency planning using th e ad9525 .................................. 45 using the ad9525 outputs for adc clock applications .... 45 lvpecl clock distribution ..................................................... 46 sync_out distribution ......................................................... 46 outline dimensions ....................................................................... 47 ordering guide ............................................................................... 47 revision history 10/12 revision 0: initial version
data sheet ad9525 rev. 0 | page 3 of 48 specifications typical is given for vdd 3 = 3.3 v 5%; vdd 3 vdd_cp 5.25 v; t a = 25c; out_ rset resistor = 4.12 k?; cp _ rset resistor (cprset) = 5.1 k?, unless otherwise no ted. minimum and maximum values are given over full vdd3 and t a (?40c to +85c) variation as listed in table 1 . ref a at 122.88 mhz, clkin freq uency = 294 9.12 mhz . conditions table 1. parameter min typ max unit test conditions/comments supply voltage vdd 3 3.3 v 3.3 v 5% vdd_cp vdd 3 5.25 v n ominally 3.3 v to 5.0 v 5% out_rset pin resistor 4.12 k? sets internal biasing currents; connect to ground cp_rset pin resistor (cprset resistor) 5.1 k? sets internal cp current range, nominally 4.8 ma (cp_ lsb = 600 a); actual current calcula ted by cp_lsb = 3.06/cp rset, connect to ground ; cprset r ange = 2 .7 k? to 10 k? temperature range, t a ?40 +25 +85 c supply current table 2. parameter min typ max unit test conditions/comments supply current for vdd3 and vdd_cp pins f clk = 2949.12 mhz; refa and refb enabled at 122.88 mh z; r dividers = 2; m divider = 2; pfd = 61.44 mhz; eight lvpecl outputs at 1474.56 mhz ; lvpecl 780 mv mode vdd3 (pin 3, pin 36, pin 41, pin 4 6 ), total supply voltage for outputs 310 369 ma outputs terminated with 50 ? to vdd3 ? 2 v vdd3 (pin 9), supply vo ltage for m divider, clk inputs and distribution 98 107 ma vdd_cp (pin 13), supply voltage for charge pump 6.6 7.6 ma vdd3 (pin 20), supply voltage for pll 53 63.4 ma vdd3 (pin 32), supply voltage for sync_out 45 54 ma power dissipation tab le 3 . parameter min typ max unit test conditions/comments power dissipation, chip does not include power dissip ated in external resistors; all lv pecl outputs terminated with 50 ? to vdd3 ? 2 v ; lvpecl 780 mv mode power - on default 782 871 mw no programming; default register values typical operation 1 1.15 1.23 w f clk = 2949.12 mhz; refa and refb enabled at 122.88 mhz; r dividers = 2; m divider = 2; pfd = 61.44 mhz; eight lvpec l outputs at 1474.56 mhz typical operation 2 1.17 1.25 w f clk = 2949.12 mhz; pll on; refa enabled at 122.88 mhz; m divider = 1; pfd = 122.88mhz; eight lvpecl outputs at 2949.12 mhz pd power - down 51 56.4 mw pd pin pul led low pd power - down, maximum sleep 13.2 19.1 mw pd pin pulled low; power - down distribution reference, reg. 0x230[1] = 1b; note that powering down distribution reference disables safe power - down mode (see pow er - down modes section) vdd_cp supply 22 25 mw pll operating; typical closed - loop configuration
ad9525 data sheet rev. 0 | page 4 of 48 parameter min typ max unit test conditions/comments power deltas, individual functions power delta when a function is enabled/disabled m divider on/off 5 8.7 mw m divider bypassed p di vider on/off 3 5.7 mw p divider bypassed b divider on/off 16 23.1 mw b divider bypassed refb on 15 25 mw delta from powering down refb differential input pll on/off 254 300.5 mw pll off to pll on, normal operation; no reference enabled one channel , one driver 159 184 mw no lvpecl output on to one lvpecl output on at 2949.12 mhz; same output pair one channel , two drivers 288 337 mw no lvpecl output on to two lvpecl output s on at 2949.12 mhz; same output pair r efa and refb input characteristics t able 4. parameter min typ max unit test conditions/comments differential mode (refa, refa ; refb, refb ) differential mode (can accommodate single - ended input by ac grounding un used input) inp ut frequency 0 500 mhz frequencies below ~1 mhz should be dc - coupled; be careful to match self - bias voltage input sensitivity 200 mv p -p frequency at 122.88 mhz self - bias voltage, refa and refb 1.52 1.65 1.78 v self - bias voltage of refa and refb input s 1 self - bias voltage, refa and refb 1.38 1.50 1.61 v self - bias voltage of refa and refb inputs 1 input resistance, refa and refb 4.5 4.7 4.9 k? self - biased 1 input resistance, refa and refb 4.9 5.2 5.4 k? self - biased 1 duty cycle duty cycle bounds are set by pulse width high and pulse width l ow pulse width low 500 ps pulse width high 500 ps 1 the differential pairs of refa and refa , refb and refb self - bias points are offset slightly to avoid chatter on an open input condition. ref c input characteristic s table 5. parameter min typ max unit test conditions/comments ref c input input frequency range 300 mhz dc - coupled input (not self - biased) input high voltage 2.0 v input low voltage 0.8 v input current 1 a duty cycle duty cycle bounds are set by pulse width high and pulse width low pulse width low 1 ns pulse width high 1 ns
data sheet ad9525 rev. 0 | page 5 of 48 clock inputs table 6. parameter min typ max unit test conditions/comments input frequency 0 3.6 ghz frequencies below ~1 mhz should be dc - coupled; be careful to match self - bias voltage input sensitivity 150 mv p -p measured at 3.1 ghz input level 2 v p -p larger voltage swings can turn on the protection diodes and can degrade jitter performance input common - mode voltage, v cm 1.55 1.64 1.74 v self - biased; enables ac coupling input common - mode range, v cmr 1.3 1.8 v with 200 mv p - p signal applied; dc - coupled inpu t resistance 6.7 7 7.4 k? self - biased input capacitance 2 pf pll characteristics table 7. parameter min typ max unit test conditions/comments phase/frequency detector (pfd) pfd input frequency 125 mhz antibacklash pu lse width = 1.3 ns, 2.9 ns 45 mhz antibacklash pulse width = 6.0 ns charge pump (cp) vdd_cp (pin 13); v cp is the voltage of the charge pump pin ( c p, pin 14) i cp sink/source programmable high value 4.5 4.9 5.4 ma with cprset = 5.1 k?; higher i cp is possible by changing cprset; v cp = vdd_cp/2 v low value 0.57 0.61 0.67 ma with cprset = 5.1 k?; lower i cp is possible by changing cprset, v cp = vdd_cp/2 v absolute accuracy 2.5 % v cp = vdd_cp/2 v cprset range 2.7 10 k? i cp high impedance mod e leakage 3.5 a vdd_cp = 5 v sink - and - source current matching 2 % 0.5 v < v cp < vdd_cp ? 0.5 v i cp vs. v cp 1.5 % 0.5 v < v cp < vdd_cp ? 0.5 v i cp vs. temperature 2 % v cp = vdd_cp/2 v p divider (part of n divider) input frequency p = 1 1500 mhz input frequency p = 2 3000 mhz input frequency p = 3 3600 mhz input frequency p = 4 3600 mhz input frequency p = 5 3600 mhz input frequency p = 6 3600 mhz b divider (part of n divider) input frequency 1500 mhz b coun ter input frequency (n divider input frequency divided by p) m divider input frequency 3600 mhz noise characteristics in - band phase noise of the charge pump/ phase frequency detector (in - band means within the lbw of the pll) pll in - ban d phase noise floor is estimated by measuring the in- band phase noise at the output of the vco and subtracting 20 log(n) (where n is the value of the n divider) at 61.44 mhz pfd frequency ?144 dbc/hz at 122.88 mhz pfd frequency ?141 dbc/hz pll fig ure of merit (fom) ?222 dbc/hz reference slew rate > 0.25 v/ns; fom +10 log (f pfd ) is an approximation of the pfd/cp in - band phase noise (in the flat region) inside the pll loop bandwidth; when running closed loop, the phase noise, as observed at the vc o output, is increased by 20 log(n)
ad9525 data sheet rev. 0 | page 6 of 48 pll digital lock det ect table 8. parameter min typ max unit test conditions/comments pll digital lock detect window 1 signal available at the status and ref_mon pins when selected by appropr iate register settings; lock detect window settings can be varied by changing the cprset resistor lock threshold (coincidence of edges) selected by reg. 0x010[1:0] and reg. 0x01 9[1], which is the threshold for transitioning from unlock to lock low ra nge (abp 1.3 ns, 2.9 ns) 4 ns reg. 0x010[1:0] = 00b, 01b,11b; reg. 0x019[1] = 1b high range (abp 1.3 ns, 2.9 ns) 7 ns reg. 0x010[1:0] = 00b, 01b, 11b; reg. 0x019[1] = 0b high range (abp 6.0 ns) 3.5 ns reg. 0x010[1:0] = 10b; reg. 0x019[1] = 0b unlo ck threshold (hysteresis) 1 selected by reg. 0x017[1:0] and reg. 0x019[1 ], which is the threshold for transitioning from unlock to lock low range (abp 1.3 ns, 2.9 ns) 8.3 ns reg. 0x010[1:0] = 00b, 01b, 11b; reg. 0x01 9[1] = 1b high range (abp 1.3 ns, 2.9 ns) 16.9 ns reg. 0x010[1:0] = 00b, 01b, 11b; reg. 0x019[1] = 0b high range (abp 6.0 ns) 11 ns reg. 0x010[1:0] = 10b; reg. 0x019[1] = 0b 1 for reliable operation of the digital lock detect, the period of the pfd frequency must be greater than the unlock - after - lock time. clock outputs table 9. parameter min typ max unit test conditions/comments lvpecl clock outputs output frequency, maximum 3.6 ghz rise time/fall time (20% to 80%) 105 162 ps duty cycle input duty cycle = 50/50 m = 1 47 50 53 % fout = 2800 mhz 45 50 55 % fout < 3000 mhz m = 2 , 4, 6 47 49 51 % fout = 1400 mhz 45 49 55 % fout < 1500 mhz m = 3, 5 32 32 33 % fout = 933.33 mhz output differential voltage, magnitude 750 830 984 mv voltage across pins, output driver static ; termination = 50 ? to vdd3 ? 2 v common - mode output vo ltage vdd3 C 1.42 vdd3 C 1.37 vdd3 C 1.32 v output driver static; vdd3 (pin 3, pin 36, pin 41, pin 4 6); termination = 50 ? to vdd3 ? 2 v
data sheet ad9525 rev. 0 | page 7 of 48 timing characteristi cs table 10. parameter min typ max unit test conditions/comments p ropagation delay, t pecl , clkin to lvpecl output termination as shown in figure 35 for all m divider values 461 522 600 ps high frequency clock distribution configuration variation with temperature 388 fs/c output skew, lvpecl outputs 1 all lvpecl outputs 13.5 25.2 ps across temperature and vdd per device temperature coefficient 14 fs/c all lvpecl outputs across multiple parts 144 ps output skew, lvpecl - to -sync_out 1 sync_out lvpecl mode all lvpecl outputs 189 298 ps across temperature and vdd per device temperature coefficient 543 fs/c all lvpecl outputs across multiple parts 417 ps sync_out cmos mode all lvpecl outputs 1.64 2.34 ns across temperature and vdd per device all lvpecl outputs across multiple parts 2.46 ns propagation delay, ref to lvpecl output 267 581 924 ps ref refers to either refa/ refa or refb/ refb pairs 1 the output skew is the difference between any two paths while operating at the same voltage and temperature. timing diagrams clk t cmos t clk t pecl 100 1 1-002 figure 2 . clk/ clk to clock output timing, m divider = 1 differential lvpecl 80% 20% t rp t fp 100 1 1-003 figure 3 . lvpecl timing, differential
ad9525 data sheet rev. 0 | page 8 of 48 clock output absolut e time jitter (clock generation using ext ernal 122.88 mhz vcxo) table 11. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 122.88 mhz vcxo (crystek cvhd -950); reference = 122.88 mhz; r divider = 1 ; lbw = 40 hz fout = 122.88 mhz 107 fs rms integration bw = 1 khz to 40 mhz 69 fs rms integration bw = 12 khz to 20 mhz fout = 61.44 mhz 108 fs rms integration bw = 1 khz to 20 mhz 107 fs rms integration bw = 12 khz to 20 mhz clock output absolute time jitter (clock generation using external 1475 mhz vco) table 12. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 1 475 mhz vco (bowei model mvco -1475); reference = 122.88 mhz; r divider = 1 ; pll lbw = 18 khz fout = 1474.56 mhz 99 fs rms integration bw = 1 khz to 100 mhz 77 fs rms integration bw = 10 khz to 100 mhz 74 fs rms integration bw = 10 khz to 40 mhz 68 fs rms integration bw = 12 khz to 20 mhz reference sideb and spurs ? 9 3 dbc 122.88 mhz fout = 245.76 mhz 104 fs rms integration bw = 1 khz to 100 mhz 87 fs rms integration bw = 10 khz to 100 mhz 75 fs rms integration bw = 12 khz to 20 mhz reference sideb and spurs ?98 dbc 122.88 mhz table 13. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 1475 mhz vco ( z- communications cro1474 - lf ); reference = 122.88 mhz; r divider = 1 ; pll l bw = 8 khz fout = 1474.56 mhz 72 fs rms integration bw = 1 khz to 100 mhz 40 fs rms integration bw = 10 khz to 100 mhz 33 fs rms integration bw = 10 khz to 40 mhz 28 fs rms integration bw = 12 khz to 20 mhz reference sideb and spurs ?94 dbc 122.88 mhz fout = 245.76 mhz 83 fs rms integration bw = 1 khz to 100 mhz 61 fs rms integration bw = 10 khz to 40 mhz 46 fs rms integration bw = 12 khz to 20 mhz reference sideb and spurs ?93 dbc 122.88 mhz
data sheet ad9525 rev. 0 | page 9 of 48 clock output absolut e time jitter (clock generation using extern al 2.05 ghz vco) table 14. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example ba sed on a typical setup using an external 2.05 mhz vco ( bowei model mvco - 2050a); reference = 122. 054215 mhz; r divider = 1 2; pll lbw = 5 khz fout = 2048.867 mhz 19 fs rms integration bw = 200 khz to 5 mhz 21 fs rms integration bw = 200 khz to 10 mhz 87 fs rms integration bw = 12 khz to 20 mhz r eference sideb and spurs ?105 dbc 10.671mhz clock output absolut e time jitter (clock generation using ext ernal 3 ghz vco) table 15. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter appl ication example based on a typical setup using an external 2950 mhz vco ( z- communications model cro - 2950); reference = 122.88 mhz; r divider = 1 fout = 2949.12 mhz; pll lbw = 7 khz 63 fs rms integration bw = 1 khz to 100 mhz 38 fs rms integration bw = 10 khz to 100 mhz 34 fs rms integration bw = 10 khz to 40 mhz 28 fs rms integration bw = 12 khz to 20 mhz reference sideb and spurs ?99 dbc 122.88 mhz fout = 1474.56 mhz; pll lbw = 7 khz 62 fs rms integration bw = 1 khz to 100 mhz 36 fs rms integration bw = 10 khz to 100 mhz 31 fs rms integration bw = 10 khz to 40 mhz 25 fs rms integration bw = 12 khz to 20 mhz refere nce sideb and spurs ?100 dbc 122.88 mhz fout = 491.52 mhz; pll lbw = 7 khz 78 fs rms integration bw = 1 khz to 100 mhz 60 fs rms integration bw = 10 khz to 100 mhz 44 fs rms integration bw = 10 khz to 40 mhz 33 fs rms integration bw = 12 k hz to 20 mhz reference sideb and spurs ? 96 dbc 122.88 mhz clock output additive phase noise (distr ibution only ; clo ck input to distribution output, including vco divider) table 16. parameter min typ max unit test conditions/com ments clk- to - lvpecl additive phase noise distribution section only; does not include pll and vco clk = 2949.12 mhz, fout = 2949.12 mhz divider = 1 at 10 hz offset ?112 dbc/hz at 100 hz offset ?122 dbc/hz at 1 khz offset ?133 dbc /hz at 10 khz offset ?141 dbc/hz at 100 khz offset ?146 dbc/hz at 800 khz offset ?148 dbc/hz at 1 mhz offset ? 148 dbc/hz at 10 mhz offset ?149 dbc/hz at 100 mhz offset ?151 dbc/hz
ad9525 data sheet rev. 0 | page 10 of 48 parameter min typ max unit test conditions/com ments clk = 1474.56 mhz, fout = 1474.56 mhz divide r = 1 at 10 hz offset ?114 dbc/hz at 100 hz offset ?125 dbc/hz at 1 khz offset ? 134 dbc/hz at 10 khz offset ?144 dbc/hz at 100 khz offset ?149 dbc/hz at 800 khz offset ?151 dbc/hz at 1 mhz offset ?151 dbc/hz at 10 mhz offs et ?154 dbc/hz clk = 122.88 mhz, fout = 122.88 mhz divider = 1 at 10 hz offset ?134 dbc/hz at 100 hz offset ?145 dbc/hz at 1 khz offset ?153 dbc/hz at 10 khz offset ?159 dbc/hz at 100 khz offset ?161 dbc/hz at 800 khz of fset ?161 dbc/hz at 1 mhz offset ?161 dbc/hz at 10 mhz offset ?161 dbc/hz pd , reset , and ref_sel pins table 17. parameter min typ max unit test conditions/comments input characteris tics logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 1 a logic 0 current pd , reset ?112 a the minus sign indicates that current is flowing out of the ad9525 , which is due to the internal pull - up resistor logic 0 current ref_sel 1 a capacitance 2 pf reset timing pulse width low 50 ns reset inactive to start of register programming 100 ns status and r ef _ mon pin s table 18. parameter min typ max unit test conditions/comments output characteristics 1 ma output load output voltage high, v oh 2.7 v output voltage low, v ol 0.4 v maximum toggle rate 200 mhz applies when mux is set t o any divider or counter output or pfd up/down pulse; usually debug m ode only; beware that spurs can couple to output when any of these pins is toggling
data sheet ad9525 rev. 0 | page 11 of 48 serial control port table 19. parameter min typ max uni t test conditions/comments cs (input) cs has an in ternal 30 k? pull - up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 2.5 a input logic 0 current ?112 a the minus sign indicates that current is flowing out of the ad9525 , which is due to the internal pull - up resistor input capacitance 2 pf sclk (input) sclk has an internal 30 k? pull - down resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 112 a input logic 0 current 1 a input capacitance 2 pf sdio (when input) input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 10 na input logic 0 current 20 na input capacitance 2 pf sdio, sdo (outpu ts) 1 ma load current output logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 31 mhz pulse width high, t high 16 ns pulse width low, t low 16 ns sdio to sclk setup, t ds 2 ns sclk to sdi o hold, t dh 1.1 ns sclk to valid sdio and sdo, t dv 12 ns cs to sclk setup and hold, t s , t h 2 ns cs minimum pulse width high, t pwh 3.6 ns
ad9525 data sheet rev. 0 | page 12 of 48 absolute maximum rat ings table 20. par ameter rating vdd3 to gnd ? 0.3 v to +3.6 v vdd_cp, cp to gnd ? 0.3 v to +5.8 v refa, refa , refb, refb , refc to gnd ? 0.3 v to vdd3 + 0.3 v out_rset to gnd ? 0.3 v to vdd3 + 0.3 v cp_rset to gnd ? 0.3 v to vdd3 + 0.3 v clkin, clkin to gnd ? 0.3 v to vdd3 + 0.3 v clkin to clkin ? 1.2 v to +1.2 v sclk, sdio, sdo, cs to gnd ? 0.3 v to vdd3 + 0.3 v out0, out0 , out1, out1 , out2, out2 , out3, out3 , out4, out4 , out5 , out5 , out6, out6 , out7, out7 , sync_out, sync_out to gnd ? 0.3 v to vdd3 + 0.3 v reset , pd , status, ref _ mon to gnd ? 0.3 v to vdd3 + 0.3 v junction temperature 1 150c storage temperature range ? 65c to +150c lead temperature (10 sec) 300c 1 see table 21 for ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. th is is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. thermal resistance table 21. thermal resistance (simulated) package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1, 2 unit 48- lead lfcsp 0 27.3 2.1 14.7 0.2 c/w 1.0 23.9 0.3 c/w 2.5 21.4 0.4 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883 , method 1012.1. 4 per jedec jesd51 - 8 (still air). esd caution
data sheet ad9525 rev. 0 | page 13 of 48 pin configuration and function descripti ons 1 2 3 vdd3 out7 out7 4 ref_mon 5 vdd3 6 sync_out 7 sync_out 24 reset 23 pd 22refb 21refb 20vdd3 19gnd 18re fa 17re fa 16 cp_rset 15gnd 14 cp 13 vdd_c p 44 out3 45 out3 46 vdd3 47 out2 48 out2 43 out4 42 out4 41 vdd3 40 out5 39 out5 38 out6 37 out6 top view (not to scale) ad9525 25 ref_se l 26 refc 27 sta tus 28 vdd3 29 clkin 30 clkin 31 out_rset 32 out0 33 out0 34 vdd3 35 out1 36 out1 8 gnd 9 sdo 10 sdio 11 sclk 12 cs notes 1. the exposed p ad is a ground connection on the chi p th at must be soldered t o the analog ground of the pcb to ensure proper functionalit y and he a t dissi pa tion, noise, and mechanica l strength benefits. 100 1 1-004 figure 4. pin configuration table 22 . pin function descriptions pin no. mnemonic type d escription 1 out1 o lvpecl complementary output 1 . 2 out1 o lvpecl output 1 . 3 vdd3 p 3.3 v power supply for channel out0 and channel out1 . 4 out0 o lvpecl complementary output 0 . 5 out0 o lvpecl output 0 . 6 out_rs et o clock distribution current set resistor. connect a 4.12 k ? resistor from this pin to gnd. 7 clkin i along with clkin , this pin is the differential input for the clock distribution section. 8 clkin i along with clk in, this pin is the differential input for the clock distribution section. if a single - ended input is connected to the clkin pin, connect a 0.1 f bypass capacitor from clkin to ground. 9 vdd3 p 3.3 v power supply for clk inputs, m d ivid er, and output distribution . 10 status o lock detect and other status signals. 11 ref c i reference clock input c. this pin is a cmos input for the pll reference. 12 ref_sel i reference input select. logic h igh = ref b . no internal pull - up or pull- down re sistor on this pin. 13 vdd_cp p po wer supply for charge pump (cp). vdd3 < vdd_cp < 5.0 v. vdd_cp must still be connected to 3.3 v if the pll is not used. 14 cp o charge pump (output). this pin connects to an external loop filter. this pin can be left unc onnected if the pll is not used. 15 gnd gnd ground for charge pump vdd_cp s upply. connect to g round . 16 cp_rset o charge p ump current set resistor. connect a 5.1 k ? resis tor from this pin to gnd. this resistor can be omitted if the pll is not used. 17 refa i reference clock input a. along with refa , this pin is the differential input for the pll re ference. 18 refa i reference clock input a. alo n g with refa, this pin is the differential input for the pll reference. 19 gnd gnd ground for pll power s upply. connect to ground . 20 vdd3 p 3.3 v power supply for pll. 21 refb i referen ce clock input b. along with refb , this pin is the differential input for the pll reference. 22 refb i reference clock input b. along with refb, this pin is the differential input for the pll reference. 23 pd i chip power - down, active low. this pin has an internal 30 k? pull - up resistor. 24 reset i chip reset, active low. this pin has an internal 30 k? pull - up resistor. 25 cs i serial control port chip select; active low. this pin has an internal 30 k? pull - up resistor. 26 sclk i serial control port clock signal. this pin has an internal 30 k? pull - down resistor. 27 sdio i serial control port bidirectional serial data in/out.
ad9525 data sheet rev. 0 | page 14 of 48 pin no. mnemonic type d escription 28 sdo i serial control port unidirectional serial data out. 29 gnd gnd connect to g round . 30 sync_ out o lvpecl complementary output for programmable sync signal . 31 sync_out o lvpecl output for programmable sync signal . 32 vdd3 p power supply for sync_out d river . 33 ref _ mon o reference monitor (output). this pin has multiple selectable outputs. 34 out7 o lvpecl complementary output 7 . 35 out7 o lvpecl output 7 . 36 vdd3 p 3.3 v power supply for channel out 6 and channel out 7. 37 out 6 o lvpecl complementary output 6 . 38 out6 o lvpecl output 6 . 39 out5 o lvpecl complementary output 5 . 40 out5 o lvpecl output 5 . 41 vdd3 p 3.3 v power supply for channel out4 and channel out5 . 42 out4 o lvpecl c omplementary output 4 . 43 out4 o lvpecl output 4 . 44 out3 o lvpecl complementary output 3 . 45 out3 o lvpecl output 3 . 46 vdd3 p 3.3 v power supply for channel out2 and channel out3 . 47 out2 o lvpecl complementary ou tput 2 . 48 out2 o lvpecl output 2 . ep ep, gnd gnd exposed paddle. the exposed pad is a ground connection on the chip that must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
data sheet ad9525 rev. 0 | page 15 of 48 typical performance characteristics 0 1 2 3 4 5 6 0 1 2 3 4 current from c p pin (ma) volt age on c p pin (v) pump up pump down 100 1 1-005 figure 5 . charge pump characteristics at vdd_cp = 3.3 v 0 1 2 3 4 5 6 0 1 2 3 4 5 6 current from c p pin (ma) volt age on c p pin (v) pump up pump down 100 1 1-006 figure 6 . charge pump characteristics at vdd_cp = 5.0 v ?222.5 ?222.0 ?221.5 ?221.0 ?220.5 ?220.0 ?219.5 ?219.0 ?218.5 ?218.0 ?217.5 0 0.2 0.4 0.6 0.8 1.0 1.2 pll figure of merit (dbc/hz) slew r a te of re fa (v/ns) 100 1 1-007 figure 7. pll figure of merit (fom) vs. slew rate at refa ch1 500mv ? 2.5ns/div 40.0gs/s a ch1 40.0mv 1 100 1 1-008 figure 8 . lvpecl output (differential) at 122.88 mhz 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 0 500 1000 1500 2000 2500 3000 differentia l vo lt age swing (v p-p) frequenc y (mhz) 96 0mv p-p 78 0mv p-p 60 0mv p-p 40 0mv p-p 100 1 1-009 figure 9 . lvpecl differential voltage swing vs. frequency
ad9525 data sheet rev. 0 | page 16 of 48 10 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100 1k 10m 100k 1m 10k 20m phase noise (dbc) frequency (hz) 100 1 1-010 figure 10 . additive (residual) phase noise, clk - to - lvpecl at 122.88 mhz, divide - by -1 10 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100 1k 10m 100k 1m 10k 100m phase noise (dbc) frequency (hz) 100 1 1-0 11 figure 11 . additive (residual) phase noise, clk - to - lvpecl at 1500 mhz, divide - by -1 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) ?30 ?50 ?70 ?90 ?110 ?130 ?150 100 1 1-012 1: 1khz, ?103.4dbc/hz 2: 10khz, ?109.2dbc/hz 3: 100khz, ?130.6dbc/hz 4: 800khz, ?147.3dbc/hz 5: 1mhz, ?148.5dbc/hz 6: 10mhz, ?152.9dbc/hz 7: 100mhz, ?154.4dbc/hz noise: analysis range x: start 1khz stop 100mhz intg noise: ?63.7dbc/100mhz rms noise: 919.9rad 52.7mdeg rms jitter: 99.3fsec 1 2 3 4 5 7 6 figure 12 . phase noise (absolute), external vco (bowei model mvco - 1475) at 1474.56 mhz; pfd = 122.88 mhz; lbw = 1 8 khz; lvpecl output = 1474.56 mhz ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) ?30 ?50 ?70 ?90 ?110 ?130 ?150 100 1 1- 1 12 1: 1khz, ?96.0dbc/hz 2: 10khz, ?106.3dbc/hz 3: 100khz, ?137.2dbc/hz 4: 800khz, ?144.5dbc/hz 5: 1mhz, ?144.6dbc/hz 6: 10mhz, ?147.7dbc/hz 7: 100mhz, ?152.4dbc/hz noise: analysis range x: start 1khz stop 100mhz intg noise: ?59.5dbc/100mhz rms noise: 1.5mrad 86.2mdeg rms jitter: 81.2fsec 1 2 3 4 5 7 6 figure 13 . phase noise (absolute), external vco (z - communications model cro - 2950) at 2949.12 mhz; pfd = 122.88 mhz; lbw = 8 k hz; lvpecl output = 2949.12 mhz 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) 100 1 1-013 1: 1khz, ?109.3936dbc/hz 2: 10khz, ?113.5616dbc/hz 3: 100khz, ?143.3042dbc/hz 4: 800khz, ?150.5212dbc/hz 5: 1mhz, ?150.7666dbc/hz 6: 10mhz, ?152.9127dbc/hz 7: 100mhz, ?156.0506 dbc/hz 1 2 3 4 5 7 6 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 ?30 ?50 ?70 ?90 ?110 ?130 ?150 noise: analysis range x: start 1khz stop 100mhz intg noise: ?67.8dbc/100mhz rms noise: 575.9rad 33.0mdeg rms jitter: 62.2fsec figure 14 . phase noise (absolute), external vco (z - communications model cro - 2950) at 2949.12 mhz; pfd = 122.88 mhz; lbw = 8k hz; lvpecl output = 1474.56 mhz 100 1k 10m 100k 1m 10k phase noise (dbc) frequency (hz) 100 1 1-014 1: 1khz, ?136.9dbc/hz 2: 10khz, ?150.3dbc/hz 3: 100khz, ?156.4dbc/hz 4: 800khz, ?161.1dbc/hz 5: 1mhz, ?160.9dbc/hz 6: 10mhz, ?161.7dbc/hz 7: 100mhz, ?161.8dbc/hz noise: analysis range x: start 12khz stop 20mhz intg noise: ?88.6dbc/20.0mhz rms noise: 52.8rad 3.0mdeg rms jitter: 68.4fsec 1 2 3 4 5 7 6 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 ?30 ?50 ?70 ?90 ?110 ?130 ?150 figure 15 . phase noise (absolute), external vcxo (122.88 mhz vcxo ) (crystek cvhd - 950); reference = 122.88 mhz; r divider = 1); lbw = 40 hz; lvpecl output = 122.88 mhz
data sheet ad9525 rev. 0 | page 17 of 48 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) 100 1 1-015 1: 1khz, ?85.0dbc/hz 2: 10khz, ?99.3dbc/hz 3: 100khz, ?123.0dbc/hz 4: 800khz, ?140.7dbc/hz 5: 1mhz, ?142.0dbc/hz 6: 10mhz, ?149.0dbc/hz 7: 100mhz, ?153.3dbc/hz noise: analysis range x: start 1khz stop 100mhz intg noise: ?62.1dbc/19.7mhz rms noise: 1.1rad 63.6mdeg rms jitter: 86.2fsec 1 2 3 4 5 7 6 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 ?30 ?50 ?70 ?90 ?110 ?130 ?150 figure 16 . phase noise (absolute), external vco 2.0 5 ghz vco (bowei model mvco - 2050a); at 2050 mhz; reference = 122.054215 mhz; r divider = 12 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?170 ?180 ?30 ?50 ?70 ?90 ?110 ?130 ?150 100 1k 10m 100m 100k 1m 10k phase noise (dbc) frequency (hz) 100 1 1-017 1 2 3 4 5 7 6 figure 17 . phase noise (absolute), external vco (z - communications cro1474 - lf) at 1474.56 mhz; pfd = 122.88 mhz; lbw = 15 khz; lvpecl output = 1474.56 mhz
ad9525 data sheet rev. 0 | page 18 of 48 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of var iation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. t his phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power sp ectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency fro m the sine wave (carrier). the value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is m eaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over that frequency offset interval ; it can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs , dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat differe nt ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 s igma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performan ce from a given converter. additive phase noise additive phase noise is t he amount of phase noise that can be attributed to the devic e or subsystem being measured. the phase noise of any external oscillators or c lock sources is subtracted, making it possib le to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one ele ment dominates the system phase noise. when there are multiple contributo rs to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that can b e attri - but ed to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted . this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunct ion with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
data sheet ad9525 rev. 0 | page 19 of 48 detailed block diagr am refb s pfd charge pump m 1, 2, 3, 4, 5, 6 p 1, 2, 3, 4, 5, 6 b 1, 2, 3... 32 n r a 1, 2, 3... 32 sync generation nine differential outputs lvpecl status monitor control interface (spi) ad9525 refa refa refb r b 1, 2, 3... 32 r c 1, 2, 3... 127 sync_out sync_out refc reset pd out7 out7 cp cp_rset clkin clkin vdd_cp out6 out6 out5 out5 out4 out4 out3 out3 out2 out2 out1 out1 out0 out0 status ref_mon cs sclk sdo sdio ref_sel 100 1 1-018 figure 18 . detailed block diagram
ad9525 data sheet rev. 0 | page 20 of 48 theory of operation the ad9525 pll is useful for generating clock frequencies from a supplied reference frequency. in addition, the pll can be used to clean up jitter and phase noise on a noisy reference. the exact choice of pll parameters and loop dynamics is application specific. the flexibility and depth of the ad9525 pll allow the part to be tailored to functi on in many different applications and signal environments. the ad9525 includes on - chip pll blocks that can be used with an external vco or vcxo to create a complete phase - locked loop. the pll requires an extern al loop filter, which usually consists of a small number of capacitors and resistors. the configuration and components of the loop filter help to establish the loop bandwidth and stability of the pll. the external loop filter that must be connected between cp and the tuning pin of the vco/ vcxo. this loop filter determines the loop bandwidth and stability of the pll. make sure to select the proper pfd polarity for the vco/vcxo being used. the ad9525 can also be c onfigured as a clock distribution by shutting down the pll and using clkin and clkin as the input. the m divider can be used to divide the input frequency down to the desired output frequency to each of the eight lvpecl outputs. configura tion of the pll configuration of the pll is accomplished by programming the various settings for the r divider, n divider, pfd polarity, and charge pump current. the combination of these settings and the loop filter determines the pll loop bandwidth and p ll stability . these are managed through programmable register settings and by the design of the external loop filter. successful pll operation and satisfactory pll loop performance are highly dependent on proper configuration of the pll settings, and the design of the external loop filter is crucial to the proper operation of the pll. adisimclk ? is a free program that can help with the design and exploration of the capabilities and features of the ad9525 , incl uding the design of the pll loop filter. the ad9516 model found in the latest adisimclk version can be used for modeling the ad9525 loo p filter. it is available at www .analog.com/clocks . phase frequency detector (pfd) the pfd takes inputs from the r divider and the n divider and produces an output proportional to the phase and frequency difference between them. the pfd includes a programmable delay element that control s the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the antibacklash pulse width is set by register 0x01 0[1:0 ]. an important limit to keep in mind is the maximum frequency allowed into the pfd. the maximum input frequency into the pfd is a function of the antibacklash pulse setting, as specified in the phase/frequency detector (pfd) parameter in t able 7 . charge pump (cp ) the charge pump is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs and tells the cp to pump up or pump down to charge or discharge the integrating node (part of the loop filter). the integrated and filt ered cp current is transformed into a voltage that drives the tuning node of the external vco to move the vco frequency up or down. the cp can be set for high impedance (allows holdover operation), for normal operation (attempts to lock the pll loop), for pump - up, or for pump - down (test modes). the cp current is programmable in eight steps . the exact value of the cp current lsb is set by the cprset resistor, which is nominally 5.1 k?. the actual lsb current can be calculated by cp_ lsb = 3.06/cprset . pll external loop filter an example of an external loop filter for the pll is shown in figure 19. a loop filter must be calculated for each desired pll configuration. the values of the components depend on the vco frequency, the k vco , the pfd frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. the loop filter affects the phase noise, the loop settling time, and the loop stability. a basic knowledge of pll theory is necessary for understanding loop filter design. adisimclk can help with the calculation of a loop filter according to the application requirements. pll reference inputs the ad9525 features two fully differential pll reference input circuit s. the differential inputs are self - biased, allowing for easy ac coupling of input signa ls. all pll reference inputs are off by default. t he self - bias level of the two sides is offset slightly to prevent chattering of the input buffer when the reference is ac coupled and is slow or missing. the input offset increases the voltage swing require d of the driver to overcome the offset. the input frequency range and common - mode voltages for the reference inputs are specified in t able 4 . the reference input rec eiver is powered down when the pll is powered down. it is pos sible to dc couple to these inputs. if the differential reference input is driven by a single - ended signal, the unused side ( ref a or ref b ) should be decoupled via a suitable capacitor to a quiet ground. the ad9525 provides a third single - ended cmos reference input referred to as refc.
data sheet ad9525 rev. 0 | page 21 of 48 reference switchover the ad9525 supports two separate differential reference input s. manual switc hover is performed between these inputs either through register 0x01a or by using the ref_sel pin. this feature supports networking and other applications that require redundant references. manual switchover requires that a clock be present on the referen ce input that is being switched to or that the switchover deglitching feature be disabled ( register 0x01a[4 ]). reference divider s r the reference inputs are routed to their respective divider, r. r can be set to any value from 1 to 32 (both r = 0 and r = 1 give divide - by - 1.) . the division is set by the values of r lo w and r hi gh . t he divider can be bypassed (equivalent to divide - by -1 , divider circuit is powered down) by setting the bypass bit. for each r divider , the frequency division ( r x ) is set by the va lues of r lo w and r hi gh (four bits each, representing decimal 0 to decimal 15), where number of low cycles = r lo w + 1 number of high cycles = r hi gh + 1 the high and low cycles are cycles of the clock signal currently routed to the input of the r. when a div ider is bypassed, r x = 1. otherwise, r x = (r hi gh + 1) + ( r lo w + 1) = r hi gh + r lo w + 2. this allows each reference divider to divide by any integer from 1 to 32. the output of the r divider goes to a mux to select one of the references to the pfd inputs. th e frequency applied to the pfd must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see table 7 ). the r divider has its own reset. the r divider can also be reset using the shared rese t bit of the r and b counters . this reset bit is not self -clearing. the r divider in the refc path has a division ratio programmable from 1 to 127. vco/vcxo, m and n feedback divider s the feedback division is the product of the m divider and the n divider . the n divider is a combination of a prescaler (p) and a b divider . f vco = (f ref / r ) n m where : m = 1, 2, 3, 4, 5, or 6. n = (p b ). p = 1, 2, 3, 4, 5, or 6. b = 1, 2, 3, or 32. m divider the m divider is a fixed divide (fd) of 1, 2, 3, 4, 5 , or 6. the maximum input frequency to the m counter is reflected in the maximum clkin input frequency specified in table 6 . the m d i vider provides frequency division between the clk in input and the n feedback divider and clock distribut ion output channels . the m divider can also be set to static, which is useful for applications where the only desired output frequency is the clk input frequency. p divider the p divider i s a fixed divide (fd) of 1, 2, 3, 4, 5 or 6. the maximum input fr equency to the p counter is reflected in the maximum clkin input frequency specified in t able 4 . b divider the b divider is a fixed divide (fd) of 1, 2, 3, o r 32. the maximum input frequency to the b counter is ~ 1500 mhz , as sp ecified in table 7 . this is the prescaler input frequency (external vco or clk in ) divided by the p and m counters . for example , m = 1 and p = 1 mode is not allowed if the external vco frequency is greater than 15 00 mhz because the frequency going to the b divider is too high. the division is set by the values of b lo w and b hi gh . t he divider can be bypassed (equivalent to divide - by -1 , divider circuit is powered down) by setting the bypass bit. t he frequency division, b x , is set by the values of b lo w and b hi gh (four bits each, representing decimal 0 to decimal 15), where number of low cycles = b lo w + 1 number of high cycles = b hi gh + 1 the high and low cycles are cycles of the clock signal currently routed to the input of the b divid er . when a divider is bypassed, b x = 1. otherwise, b x = (b hi gh + 1) + (b lo w + 1) = b hi gh + b lo w + 2. although manual reset is not normally required, the b counter ha s its own reset bit. no te that this reset bit is not self -clearing.
ad9525 data sheet rev. 0 | page 22 of 48 digital lock detect (d ld) by selecting the proper output through the mux on each pin, the dld functi on is available at the status and ref _ mon pins. the digital lock detect circuit indicates a lock when the time difference of the rising edges at the pfd inputs is less than a spe cified value (the lock threshold). the loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lo ck window to occur without chattering on the lock indicator. the lock detect window timing depends on the value of the cprset resistor, as well as three settings: the digital lock detect window bit ( register 0x01 9[1 ]), the antibacklash pulse width bit s (r egister 0x01 0 [1:0], see table 8 ), and the lock detect counter bits ( register 0x019[3:2 ]). the lock and unlock detection values in table 8 are fo r the nominal value of cprset = 5.11 k. doubling the cprset value to 10 k doubles the values in table 8 . a lock is not indicated until there is a programmable number of consecutive pfd cycles with a time difference that is less than the lock detect threshold. the lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. for the lock detect to work properly, the period of the pfd frequency must b e greater than the unlock threshold. the number of consecutive pfd cycles required for a lock is programmable ( register 0x018[6:5]). note that, in certain low (<500 hz) loop bandwidth, high phase margin cases , it is possible that the dld can chatter during acquisition . this is normal and occurs because the pfd inputs are moving slowly in and out of the lock/unlock window during pll loop settling. adjustment of the lock detect counter setting ( register 0x019[3:2]) can suppress this behavior. external vcxo/vc o clock input (clk in / clk in ) this differential input is used to drive the ad9525 clock distribution section. the pins are internally self - biased, and the input signal should be ac - coupled via c apacitors. the clk in / clk in input can be used either as a distribution only input (with the pll off) or as a feedback input for an external vco/vcxo using the internal pll. sample configurations are illustrated in figure 19 through figure 21 . r efer to the manufacturers recommendation for vco terminations ; a t or pi attenuator is often recommended , as illustrated in figure 19 . for operation using a cmos input, an external resistive divider is required to limit the swing on clkin (see table 6 for the maximum input rating). status monitor the ad9525 contains three frequency status monitors tha t are used to indicate if the pll reference (or references , in the case of single - ended mode) and the vco have fallen below a threshold. vco r 1 c1 ad9525 c2 c3 r2 clkin cp clkin 50? v tune 100 1 1-020 attenuator 1 1 vco manufacturers recommend either a t or pi attenuator to prevent vco pulling. refer to manufacturer?s recommendation figure 19 . clk in configured as single -e nded vco cmos vcxo r 1 c1 ad9525 c2 c3 r2 clkin cp clkin 100k? 100k? v tune 100 1 1-021 figure 20 . clk in configured as single -e nded cmos vcxo pecl vcxo 1 1 provide the proper vcxo manufacturer pecl termination. r 1 c1 ad9525 c2 c3 r2 clkin cp clkin v tune 100 1 1-022 figure 21 . clk in configured as differential lvpecl vcxo
data sheet ad9525 rev. 0 | page 23 of 48 clock distribution the ad9525 can be used only as a clock fan out buffer by disabling the pll circuit block s except for the clock distribution section. the clock distribution consists of eight lvpecl clock output drivers that share a common m divider . see the m divider section for more information on the common m divider. duty cycle and duty - cycle correction the duty cycle of the clock signal at the output of a driver is a result of either or both of the following conditions: ? the clkin , clkin input duty cycle. if the clkin , clkin input is routed directly to the output, the duty cycle of the output is the same as the clkin , clkin input. ? the m divider value . an odd m divider value results in a non - 50% duty cycle. table 23. typical output d uty cycle with m divider 1 m divider output duty cycle (%) even 50 odd = 3 33.3 odd = 5 40 lvpecl output drivers the lvpecl differential voltage (v od ) is sel ectable (from ~400 mv to 960 mv ( see bit 2 and bit 1 in register 0x0f0 to register 0x0f 7 ). th e lvpecl output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without re quiring a board layout change. each lvpecl output can be powered down or powered up , as ne eded. because of the architecture of the lvpecl output stages, there is the possibility of electrical overstress and breakdown under certain power - down conditions. for this reason, the lvpecl outputs have two power - down modes: total power - down and safe pow er - down. the primary power - down mode is the safe power - down mode. this mode continues to protect the output devices while powered down. there are three ways to activate safe power - down mode: individually set the power - down bit for each driver, power down a n individual output channel, or activate sleep mode. in total power - down mode 0x0230[1] = 1 ( p ower d own distribution reference). this mode must not be used if there is an external voltage bias network (such as thevenin equivalent termination) on the output pins that will cause a dc voltage to appear at the powered down outputs. however, total power - down mode is allowed when the lvpecl drivers are terminated using only pull - down resistors. r2 ? r1 ? sw1b sw1a sw2 qn2 qn1 n2 n1 out out 4.4ma 100 1 1-023 figure 22 . lvpecl outpu t simplified equivalent circuit sync_ out sync_out provides one lvpecl output or two cmos output signal that can used to reset or synchronize a converter. sync_out functionality block diagram is shown in figure 23 . the sync_out signal is derived from the pll phase detector reference input clock or feedback (n - divider) clock. a program - mable 16 - bit s divider further divides the selected reference clock. there are three diffe rent modes of operation for sync_out: single s hot, periodic, or pseudo random. s ync_out is retimed to the high speed clock . m d set clr q q s digital sync control m divider output n out0 to out7 sync_out cp up dn pfd select ref: ref, fb, pd digital lock detect sync enable 11 10 00 01 low ref 100 1 1-024 figure 23 . sync_out functional diagram
ad9525 data sheet rev. 0 | page 24 of 48 single shot mode in single shot mode one sync pulse occurs after writing sync enable 0x192[4] = 1. an io_update is required to complete a regis ter write. the width of the sync pulse is determined by the value of the s divider. a divider value of 0x0000 allows a pulse whose width is equal to one half period of the phase detector rate. a divider value of 0x0001 allows a pulse whose width is equal to two half periods of the phase detector rate. in single shot mo de, the sync enable bit is self - clearing and the sync circuits are ready to receive another sync enable. periodic mode in p eriodic mode , the pulse is continuous until sync enable is cleared by a register writing sync enable 0x192[4] = 0. an io_update is required to complete a register write. the width of the sync pulse is equal to one half period of the phase detector rate. the pulse repetition rate is determined by the value of the s divider. a divider value of 0x0000 allows a pulse rate equal to the phase detector rate. a divider value of 0x0001 allows a pulse rate equal to two half periods of the phase detector rate. t he sync_out signal is resampled with the out clock to ensure time alig nment and minimum output skew. there is a possibility in periodic mode that the sync_out could slip one half cycle of the out clock period. pseudor andom mode pseudo random mode is similar to periodic mode but the pulse is a pn17 sequence that is continuous unti l sync enable is cleared by a register writing sync enable 0x192[4] = 0. an io_update is required to complete a register write. the width of the sync pulse is equal to one half period the phase detector rate. the pulse repetition rate is determined by the value of the s divider . a divider value of 0x0000 allows a pulse rate equal to the phase detector rate. a divider value of 0x0001 allows pulse rate equal to two half the phase detector rate. sync_out programming the procedure to configure the sync_out depe nds on the logic requirement of the converters that require synchroniza - tion. analog devices, inc., converters are synchronized on the rise edge of the sync pulse. sync_out cmos driver the user can also configure the lvpecl sync_out as a pair of cmos outpu ts. when the output is configured as cmos, cmos output a and cmos output b are automatically turned on. either cmos output a or output b can be turned on or off independently. the user can also select the relative polarity of the cmos outputs for any combi nation of inverting and noninverting (see register 0x0f9). the user can power down each cmos output as needed to save power. the cmos driver is in tristate when it is powered down. ref clock sync_out mode = single shot s divider = 0 sync_out mode = periodic sync enable = low (single shot self clearing) io_update sync_out mode = pn17 t stop t start sync enable = high (single shot self clearing) io_update 100 1 1-025 figure 24 . sync output t iming
data sheet ad9525 rev. 0 | page 25 of 48 program: s divider, sync mode no program: sync enable sync_out control sync enable low? no end sync process lock detect = high digital lock detect is used to prevent occurence of sync if pll is unlocked enable_analog yes sync low yes sync high for s divider + 1 ref clock cycles the analog clock to the digital state machine is disabled if sync is disabled user programs register value for s divider and sync mode request sync program: io update sync enable is self clearing in single shot mode. other modes require a spi write to disable sync_out 100 1 1-026 figure 25 . sync_out flowchart reset modes the ad9525 has a power - on reset (por) and several other ways to apply a reset condition to the chip. power - on reset during chip power - up, a power - on rese t pulse is issued when vdd reaches ~2.6 v (<2.8 v) and restores the chip to the default on - chip setting. it takes ~70 ms for the outputs to begin toggling after the power - on reset pulse signal is internally generated. the default power - on state of the ad9525 is configured as a buffer. hardware reset via the reset pin reset , a hard reset (an asynchronous hard reset is executed by briefly pulling reset low), r estores the chip to the on - chip default register setting s. i t takes ~2 s for the outputs to begin toggling after reset is issued. soft reset via the serial port the serial port control register allows for a soft reset by setting bit 2 an d bit 5 in register 0x000. when bit 5 and bit 2 are set, the chip enters a soft reset mode and restores the chip to the on - chip setting, except for register 0x000. except for the self -clearing bits, bit 2 and bit 5, register 0x000 retains its previous valu e prior to reset. these bits are self - clearing. however, the self - clearing operation does not complete until an additional serial port sclk cycle occurs , and the ad9525 is held in reset until that happens .
ad9525 data sheet rev. 0 | page 26 of 48 pow er - down modes chip power - down via pd the ad9525 can be put into a power - down condition by pulling the pd pin low. power - down turns off most of the functions and currents inside the ad9525 . the chip remains in this power - down state until pd is brought back to logic high. when taken out of power - down mode, the ad9525 ret urns to the settings that were programmed into its registers prior to the power - down, unless the registers are changed by new programming while the pd pin is held low. powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the lvpecl outputs in a safe shutdown mode. the lvpecl bias currents are needed to protect the lvpecl output circuitry from damage that can be caused by certain termination and load configurations when tristated . bec ause this is not a complete power - down, it can be called sleep mode. when the ad9525 is in a pd power - down, the chip is in the following state: ? the pll is off. ? the clk in input buffer is off, b ut the clk in input dc bias circuit is on. ? t he reference input buffer is off, but the dc bias circuit is still on. ? all dividers are off. ? all lvpecl outputs are in safe off mode. ? the serial control port is active, and the chip responds to commands. pll power - down the pll section of the ad9525 can be selectively powered down. in this mode , the ad9525 can be used as a 1 to 8 clock buffer by using the clkin as the clock i nput . distribution power - down the distribution section can be powered down by writing register 0x230[ 4 ] = 1b, which turns off the bias to the distribution section. individual clock output power - down any of the clock distribution outputs can be powered down into safe power - down mode by individually writing to the appropriate registers. the register map details the individual power - down settings for each output. these settings are found in register 0x0f0[0] to register 0x0f 7 [0]. individual clock channel powe r- down any of the clock distribution channels can be powered down individually by writing to the appropriate registers. powering down a clock channel is similar to powering down an individual driver, but it saves more power because additional circuits are also powered down. powering down a clock channel also automatically powers down the drivers connected to it. the register map details the individual power - down settings for each output channel. these settings are found in register 0x 0f0 [4 ], register 0x 0f2 [4 ], register 0x0f4 [4 ], and register 0x0f6 [4 ].
data sheet ad9525 rev. 0 | page 27 of 48 serial control port the ad9525 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry - standa rd microcontrollers and microprocessors. the ad9525 serial control port is compatible with most synchronous transfer f ormats, including motorola? spi and intel? ssr protocols. the serial control port allows read/write access to all registers that configure the ad9525 . pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled down by a 30 k? resistor to ground. sdio (serial data input/output) is a dual - purpose pin that acts eith er as an input only (unidirectional mode) or as an input/ output (bidirectional mode). the ad9525 defaults to the bidirectional i/o mode ( register 0x000[7] = 0b). sdo (serial data out) is used only in the unidi rectional i/o mode ( re gi ster 0x000[7] = 1b ) as a separate output pin for reading back data. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 30 k? resistor to vs. ad9525 serial port control (spi) sclk sdo sdio cs 100 1 1-027 figure 26 . serial control port general operation of serial control port s ingle byte or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9525 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio/ sdo). by default, the ad9525 is in bidirectional mode. short instruction mode (8 - bit instruction) is not supported. on ly l ong instruction mode (16 - bit instruction ) is supported. a write or a read operation to the ad9525 is initiated by pulling cs low. the cs stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred (see table 24 ). in this mode, the cs pin can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and can go high during either part (ins tru ction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset , either by completing the remaining transfers or by returning cs low for at least one complete sclk cycle (but fewer than eight sclk cycles). raising the cs pin on a nonbyte boundary terminates the serial transfer and f lushes the buffer. in the streaming mode (see table 25 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending streaming mode. communication cycle instruction plus data there are two parts to a communication cycle with the ad9525 . the first part writes a 16 - bit instruction word into the ad9525 , coincident with the first 16 sclk rising edges. the instruction word provides the ad9525 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the ad9525 . data bits are registered on the rising edge of sclk. the length of the transfer (one, two, or three bytes or streaming mode) is indicated by two bits ( [ w1:w0 ] ) in the instruction byte. when the transfer is one, two, or th ree bytes but not streaming, cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle) . when the bus is stalled, the serial transfer resumes when cs is lowe red. raising the cs pin on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or blank registers, and the user can write 0x00 to the reserved register addresses . because data is w ritten into a seria l control port buffer area, not directly into the actual control registers of the ad9525 , an additional operation is needed to transfer the serial control port buffer contents to the actual c ontrol registers of the ad9525 , thereby causing them to become active. the update registers operation (io_update) consists of setting register 0x232[0] = 1b (this bit is self - clearing). any number of bytes of d ata can be changed before executing an update registers. the update registers operation simultaneously actuates all register changes that have been written to the bu ffer since any previous update.
ad9525 data sheet rev. 0 | page 28 of 48 read the ad95 25 supports only the long instruction mode. if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3 as determined by [ w1:w0 ]. if n = 4, the read o peration is in streaming mode, continuing until cs is raised. streaming mode does not skip over reserved or blank registers. the readbac k data is valid on the falling edge of sclk. the default mode of the ad9525 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the ad9525 to unidirectiona l mode ( register 0x000[7] = 1 and register 0x000[0] = 1). in unidirectional mode, the readback data appears on the sdo pin. a readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see figure 27 ). readback of the buffer or active registers is controlled by register 0x004[0]. the ad9525 uses register address 0x000 to register address 0x232 . serial control port buffer registers update registers write register 0x232 = 0x001 to update registers active registers sclk/scl sdo sdio/sda cs 100 1 1-028 figure 27 . relationship between serial control port buffer registers and active registers the instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the ne xt two bits ([ w1:w0 ] ) indicate the length of the transfer in bytes. the final 13 bits are the address ( [ a12:a0 ] ) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes o f data indicated by bits[ w1:w0] ( see table 24 ). table 24 . byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. only bits[a9:a0] are needed to cover the range of the 0x232 registers used by the ad9525 . bits[a12:a10] must always be 0b. for multibyte transfe rs, this address is the starting byte address. in msb first mode, subsequent bytes dec rement the address. msb/lsb first transf ers the ad9525 instruction word and byte data can be msb first or lsb first. any da ta written to register 0x000 must be mirrored; the upper four bits ( bits [7:4]) must mirror the lower four bits ( bits [3:0]). this makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, see the default setting for r egister 0x000, which mirrors bit 4 and bit 3. this sets the long instruction mode, which is the default and the only mode that is supported. the default for the ad9525 is msb first. when lsb first is set by r egister 0x000[1] and register 0x000[6], it takes effect immediately because it affects only the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be writ ten from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow , in order , from the high addres s to the low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb fi rst format start with an instruction byte that includes the register address of the least significant data byte , followed by multiple data bytes. in a multibyte transfer cycle, the internal byte address generator of the serial port increments for each byte . the ad9525 serial control port register address decrements from the register address just written toward register 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward register 0x232 for multibyte i/o operations. streaming mode always terminates when it reaches register 0x232. note that unused addresses are no t skipped during multibyte i/o operations. table 25 . streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x230, 0x231, 0x232, stop msb first decrement 0x001, 0x000, 0x232, stop
data sheet ad9525 rev. 0 | page 29 of 48 table 26 . serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 = 0 a11 = 0 a10 = 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 100 1 1-029 figure 28 . serial control port write msb first, 16 - bit instruction, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 100 1 1-030 figure 29 . serial control port read msb first, 16 - bit instruction, four bytes of data t s don't care don't care w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 100 1 1-031 figure 30 . serial control port write msb first, 16 - bit instruction, timing measurements data bit n ? 1 data bit n cs sclk sdio sdo t dv 100 1 1-032 figure 31 . timing diagram for serial control port register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 100 1 1-033 figure 32 . serial control port write ls b first, 16 - bit instruction, two bytes of data
ad9525 data sheet rev. 0 | page 30 of 48 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 100 1 1-034 figure 33 . serial control port timing write table 27 . serial control port timing parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between the cs falling edge and sclk rising edge (start of communication cycle) t c setup time between sclk rising edge and the cs rising edge (end of communication cycle) t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 31 )
data sheet ad9525 rev. 0 | page 31 of 48 cont rol registers control register map overview register addresses that are not listed in table 28 are not used, and writing to those registers has no effect. registers that are marked as reserved should never have their values chang ed. when writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. table 28. control register map reg. addr . (hex) register name (msb) bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) serial port configuration 0x000 spi mode serial port configuration sd0 a ctive lsb f irst/ address increase soft r eset don't c are don't c are soft r eset lsb f irst / address increase sd0 a ctive 0x00 don't c are don't c are soft r eset don't c are don't c are soft r eset don't c are don't c are 0x00 0x004 readback c ontrol don't c are don't c are don't c are don't c are don't c are don't c are don't c are read b ack active r egs 0x00 pll configuration 0x010 pfd c harge p ump pfd polarity cp current , bits [ 2:0 ] cp mode , bits [ 1:0 ] anti backlash pulse width , bits [ 1:0 ] 0x7d 0x011 r dividers refb divider output high cycles, bits[3:0] refb divider output low cycles, bits[3:0] 0x00 0x012 refa divider output high cycles, b its[3:0] refa divider output low cycles, bits[3:0] 0x00 0x013 b divider b divider output high cycles, bits[3:0] b divider output low cycles, bits[3:0] 0x00 0x014 n d ivider don't c are don't c are b d ivider b ypass r ef b d ivider b ypass r efa divider bypass p d ivider p rescaler , bits [ 2:0 ] 0x00 0x015 resets don't care reserved reserved reserved b divider reset refb divider reset refa divider reset reset all dividers 0x00 0x016 ref c r ef c e nable r ef c d ivider , bits [ 6:0 ] 0x00 0x017 status p in charge p ump pin to v dd_cp/2 s tatus p in divider e nable s tatus output select , bits [ 5:0 ] 0x00 0x018 ref_mon pin control dont care dont care dont care ref_mon pin control, bits[4:0] 0x00 0x019 lock d etect don't c are don't c are don't c are dont care lock detect counter , bits [1 :0 ] digital l ock det ect window digital l ock det disable 0x00 0x01a ref switchover and monitors enable fb clock present monitor enable refb present monitor enable refa present monitor disable switchover deglitch select refb (manual register mode) stay on r efb use ref_sel pin for ref erence switchover enable automatic reference switchover 0x00 0x0 1b reserved reserved = 0 reserved = 0 reserved = 0 reserved = 0 reserved = 0 reserved = 0 reserved = 0 0x00 0x0 1c pll block pd r egister n d ivider ecl 2 cmos pd n divider pd r divider b ecl 2 cmos pd r divider a ecl 2 cmos pd r divider b pd r divider a pd r chan nel b pd r chan nel a pd 0x22 0x01f pll r eadback unused unused unused selected r eference status fb c lock status r ef b status r ef a d igital lock detect (dld) n/a pecl/cmos outputs 0x0 f0 lvpecl o ut 0 dont care dont care dont care power down channel 0, channel 1 don't c are out0 pecl output l evel , bits [ 1:0 ] power down pecl d river 0x 04 0x0f1 lvpecl out1 dont care dont care dont care reserved don't care out1 pecl output level, bits [1:0 ] power down pecl driver 0x04 0x0f2 lvpecl out2 dont care dont care dont care power down channel 2, channel 3 don't care out2 pecl output level, bits [1:0 ] power down pecl driver 0x04 0x0f3 lvpecl out3 dont care dont care dont care reserved don't care out3 pecl output level, bits [1:0 ] power down pecl driver 0x04
ad9525 data sheet rev. 0 | page 32 of 48 reg. addr . (hex) register name (msb) bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) 0x0f4 lvpecl out4 don't care don't care don't care power down channel 4, channel 5 don't care out4 pecl output level, bits[1:0] power down pecl driver 0x04 0x0f 5 lvpecl out5 don't care don't care don't care reserved don't care out5 pecl output level, bits[1:0] power down pecl driver 0x04 0x0f6 lvpecl out6 don't care don't care don't care power down channel 6, channel 7 don't care out6 pecl output level, bits[1:0 ] power down pecl driver 0x04 0x0f7 lvpecl out7 don't care don't care don't care reserved don't care out7 pecl output level, bits[1:0] power down pecl driver 0x04 0x0f8 sync output don't care don't care don't care power down sync channel don't care sync_ out pecl output level, bits[1:0] power down pecl driver 0x10 0x0f9 sync output , other control don't care don't care don't care polarity cmos mode enable cmos drivers, bits[1:0] cmos mode sync out resampling edge select 0x00 0x0 fa drivers r eserved don't c are don't care don't care don't care don't care don't care don't care don't care 0x00 sync control 0x190 sync c lock s divider sync clock s divider , bits [7:0] 0x00 0x191 sync c lock s divider sync clock s divider , bits [15:8] 0x00 0x192 sync c lock c ontrol don't care don't care don't care sync e nable sync s ource , bits [ 1:0 ] sync m ode , bits [ 1:0 ] 0x00 vco, reference and clk1 inputs 0x1e0 vco d ivider don't care don't care don't care don't care don't care m divider, bits[2:0] 0x00 other 0x230 power -down don't care don't care don't care dist all power - down clkin p ower - down m divider p ower - down distribution reference power -d own pll p ower - down 0x00 0x232 io_update don't care don't care don't care don't care don't care don't care don't care io_update 0x00
data sheet ad9525 rev. 0 | page 33 of 48 register map descrip tions table 29 through table 49 provide a detailed description of each of the control register functions. the registers are listed by hexadecimal address. table 29 . spi mode serial port configuration reg . addr . (hex) bits bit name description 0x 000 7 sdo active selects unidirectional or bidirectional data transfer mode. 0: sdio pin used for write and read; sdo is high impedance (default). 1: sdo used for read; sdio used for write; unidirectional mode. 6 lsb first/address increase spi msb or lsb data orientation. (this register is ignored in i 2 c mode.) 0: data - oriented msb first; addressing decrements (default). 1: data - oriented lsb first; ad dressing increments. 5 soft reset soft reset. 1 (self - clearing) : s oft reset; restores default values to internal registers. 4 unused unused . [3:0] mirror[7:4] bits[3:0] should always mirror bits[7:4] so that it do es not matter whether the part i s in msb or lsb first mode (see register 0x000[6]). set bits as follows: bit 0 = bit 7 bit 1 = bit 6 bit 2 = bit 5 bit 3 = bit 4 0x004 0 read back active registers select register bank used for a readback. 0: read s back buffer regist ers (default). 1: read s back active registers. table 30. pfd charge pump reg. addr . (hex) bits bit name description 0x 010 7 pfd polarity sets the pfd polarity. 0: positive (higher control voltage produ ces higher frequency) (default). 1: negative (higher control voltage produces lower frequency). [6:4] cp current charge pump current (with cprset = 5.1 k?). bit 6 bit 5 bit 4 i cp (ma) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) [3:2] cp mode charge pump operating mode. bit 3 bit 2 charge pump mode 0 0 high impedance state 0 1 force source current (pump - up) 1 0 force sink current (pump - down) 1 1 normal o peration (default ) [1:0] antibacklash pulse width see table 7 for the maximum operating frequency for each setting . bit 1 bit 0 antibacklash pulse width mode (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9
ad9525 data sheet rev. 0 | page 34 of 48 table 31. r efa, refb, refc, b, n, and p dividers reg. addr . (hex) bits bit name description 0x 011 [7:4] r ef b d ivider output high cycles divider high cycle w ord. normally set to one - half desired divider division minus one: for example, d/2 C 1; th erefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the divider output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). [3:0] refb d ivide r output low cycles divider low cycle w ord. normally set to one - half desired divider division minus one: for example, d/2 C 1; therefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the divider output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). 0x012 [7:4] refa d ivider output high cycles divider high cycle w ord . normally set to one - half desired divider division minus one: for example, d /2 C 1; therefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the divider output stays low. a value of 0x7 means the divider is high for eight input clock cycles (default: 0x0). [3:0] refa d i vider output low cycles divider low cycle w ord . normally set to one - half desired divider division minus one: for example, d/2 C 1; therefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the div ider output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). 0x013 [7:4] b d ivider output high cycles divider high cycle w ord . normally set to one - half desired divider division minus one: for example, d/2 C 1; therefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the divider output stays low. a value of 0x7 means the divider is high for eight input clock cycles (default: 0x0). [3:0] b d ivi der output low cycles divider low cycle w ord . normally set to one - half desired divider division minus one: for example, d/2 C 1; therefore, for divide = 8, set to 0x03 (8/2 C 1). number of clock cycles (minus 1) of the divider input during which the divid er output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). 0x014 [7:6] dont c are dont c are . 5 b divider bypass bypasses and powers down the b divider; routes input to divider output. 0: use s div ider (default). 1: b divider is set to divide -by -1. 4 refb divider bypass bypasses and powers down the divider; routes input to divider output. 0: use s divider (default). 1: r ef b divider is set to divide -by -1. 3 refa d ivider bypass bypasses and powers down the divider; routes input to divider output. 0: use divider (default). 1: r ef a divider is set to divide -by -1. [2:0] p d ivider prescaler p d ivider value (b d ivider p rescaler). bit 2 bit 1 bit 0 divider value 0 0 0 1(defaul t) 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 static 1 1 1 static 0x015 7 dont c are dont c are . 6 reserved 0 (default). 5 reserved 0 (default). 4 reserved 0 (default). 3 b divider r eset reset s b d ivider. 0: normal operation (default). 1: hold s b d ivider in reset.
data sheet ad9525 rev. 0 | page 35 of 48 reg. addr . (hex) bits bit name description 2 refb divider r eset reset s r efb d ivider. 0: normal (default). 1: hold s r ef b d ivider in reset. 1 refa divider r eset reset s r efa d ivider. 0: normal (default). 1: hold s r efa d ivider in reset. 0 r eset all dividers reset s refa, ref b, b d ivider (b divider is part of n divider). 0: normal (default). 1: hold s r efa, ref b, b d ivider in reset. 0x 016 7 ref c e nable enables r ef c path. 0: disabled (default). 1: e nables ref c pa th . [6:0] ref c d ivider 7- bit r ef c divider. divide -by - 1 to divide -by -127. 0000000, 0000001: both divide -by -1 (default: 0x00). table 32. status pin and other reg. addr . (hex) bits bit name description 0x017 7 charge pump pin to v dd_cp/2 sets the charge pump pin to one - half of the vdd_cp supply voltage. 0: charge pump normal operation (default). 1: charge pump pin set to vdd_cp/2. 6 status pin d ivi der e nable enables status pin d ivider . 0: disabled (default). 1: enables d ivider . [5:0] status output select selects the signal that appears at the status pin. register 0x017[6] must be set to 0 to for any mode identified as lvl. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 level or dynamic signal signal at status pin 0 0 0 0 0 0 lvl ground, dc (default). 0 0 0 0 0 1 dyn n divider output. 0 0 0 0 1 0 lvl ground, dc . 0 0 0 0 1 1 lvl ground, dc . 0 0 0 1 0 0 lvl ground, dc . 0 0 0 1 0 1 dyn pfd up pulse. 0 0 0 1 1 0 dyn pfd down pulse. 0 x x x x x lvl gro und (dc); for all other cases of 0xxxxx not specified. the selections that follow are the same as for the ref _ mon pin . 1 0 0 0 0 0 lvl ground (dc). 1 0 0 0 0 1 dyn refa clock . 1 0 0 0 1 0 dyn refb clock . 1 0 0 0 1 1 dyn selected reference clock to pll. 1 0 0 1 0 0 dyn un selected reference clock to pll. 1 0 0 1 0 1 lvl both refa and refb clocks missing (active high). 1 0 0 1 1 0 lvl ground, dc . 1 0 0 1 1 1 lvl refa present (active high). 1 0 1 0 0 0 lvl refb pre sent (active high). 1 0 1 0 0 1 lvl (refa present) and (refb present).
ad9525 data sheet rev. 0 | page 36 of 48 reg. addr. (hex) bits bit name description bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 level or dynamic signal signal at status pin 1 0 1 0 1 0 lvl (dld) and (selected reference present) and (feedback clock present). 1 0 1 0 1 1 lvl feedback clock present (active high). 1 0 1 1 0 0 lvl selected reference (low: refa, high: refb). 1 0 1 1 0 1 lvl dld; active high. 1 0 1 1 1 0 lvl n/a. 1 0 1 1 1 1 lvl ground (dc). 1 1 0 0 0 0 lvl vdd3 (pll power supply). 1 1 0 0 0 1 dyn refa clock. 1 1 0 0 1 0 dyn refb clock. 1 1 0 0 1 1 dyn selected reference to pll . 1 1 0 1 0 0 dyn unselected reference to pll . 1 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 lvl both reference clocks missing; active low. 1 1 0 1 1 1 lvl refa present (active low). 1 1 1 0 0 0 lvl refb present (active low). 1 1 1 0 0 1 lvl (refa present) and (refb present) . 1 1 1 0 1 0 lvl (dld) and (selected reference present) and (feedback clock present); (active low). 1 1 1 0 1 1 lvl feedback clock present 1 1 1 1 0 0 lvl selected reference (low = refa, high = refb); active low. 1 1 1 1 0 1 lvl dld (active low). 1 1 1 1 1 0 lvl n/a. 1 1 1 1 1 1 lvl vdd3 (pll power supply).
data sheet ad9525 rev. 0 | page 37 of 48 table 33. ref _ mon pin control reg. addr . (hex) bit s bit name description 0x0 18 [7:5] dont care dont c are . [4:0] ref _ mon pin control selects the signal that is connected to the ref _ mon pin. bit 4 bit 3 bit 2 bit 1 bit 0 level or dynamic signal signal at ref _ mon pin 0 0 0 0 0 lvl ground (dc). 0 0 0 0 1 dyn refa clock . 0 0 0 1 0 dyn refb clock . 0 0 0 1 1 dyn selected reference clock to pll. 0 0 1 0 0 d yn unselected reference clock to pll . 0 0 1 0 1 lvl both reference c locks missing (active high). 0 0 1 1 0 lvl ground (dc). 0 0 1 1 1 lvl status ref a frequency (active high). 0 1 0 0 0 lvl status ref b frequency (active high). 0 1 0 0 1 lvl (status ref a frequency) and (status ref b frequency). 0 1 0 1 0 lvl (dld) and (status of sele cted reference) and (status of feedback c lock). 0 1 0 1 1 lvl sta tus of feedback c lock (active high). 0 1 1 0 0 lvl selected reference (low: re fa, high: refb). 0 1 1 0 1 lvl dld; active high. 0 1 1 1 0 lvl n/a . 0 1 1 1 1 lvl ground, dc . 1 0 0 0 0 lvl vdd3 (pll power supply). 1 0 0 0 1 dyn refa . 1 0 0 1 0 dyn refb . 1 0 0 1 1 dyn selected reference to pll . 1 0 1 0 0 dyn unselected reference to pll . 1 0 1 0 1 lvl status of selected reference (status of differential reference); active low. 1 0 1 1 0 lvl status of unselected reference (not av ailable in differential mode); active low. 1 0 1 1 1 lvl status of ref a frequency (active low). 1 1 0 0 0 lvl status of ref b frequency (active low). 1 1 0 0 1 lvl ( status of refa frequency ) and ( status of refb frequency ) . 1 1 0 1 0 lvl ( dld ) and (s tatus of sele cted reference ) and ( status of feedback c lock ) . 1 1 0 1 1 lvl status of feedback c lock (active low). 1 1 1 0 0 lvl selected reference (low: refa, high: refb); active low. 1 1 1 0 1 lvl dld (active low). 1 1 1 1 0 lvl n/a . 1 1 1 1 1 lvl vdd3 (pll power supply).
ad9525 data sheet rev. 0 | page 38 of 48 table 34. lock detect reg. addr . (hex) bit s bit name description 0x 019 [7:4] dont care dont c are . [3:2] lock detect counter required consecutive number of pfd cycles with edges inside lock detect window before the dld indicates a locked condition. bit 3 bit 2 pfd cycles to determine lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 1 digital lock detect window if the time difference of the rising edges at the inputs to the pfd is less tha n the lock detect window time, the digital lock detect flag is set. the flag remains set until the time difference i s greater than the loss - of - lock threshold. 0: high range (default). 1: lo w range. 0 digital lock detect disable digital lock detect operation. 0: normal lock detect operation (default). 1: disable s lock detect. table 35. ref erence switchover and monitors reg. addr . (hex) bit s bit name description 0x01a 7 enable feedback clock present monitor enable s feedback clock monitor. the presence of a feedback clock is checked with the selected reference to the pll. this monitor does not have a value output if there is no reference to the pll. 0: dis able s m onitor (default). 1: enable s monitor. 6 enable refb present monitor enable s reference b c lock m onitor. the presence of the r efb clock is che cked with the feedback clock to the pll. this monitor does not have a value output if there is no feedb ack clock to the pll. register 0x01c[5] = 0 (o n) for monitor to work . 0: disable s m onitor (default). 1: enable s m onitor . 5 enable r efa present m onitor enable s reference a c lock m onitor. the presence of the refa clock is che cked with the feedback clock to the pll. this monitor does not have a value output if there is no feedback clock to the pll. register 0x01c[4] = 0 (o n) for monitor to work . 0: disable s m onitor (default). 1: enable s m onitor . 4 disable switchover deglitch disables or ena bles the switchover deglitch circuit. 0: enables switchover deglitch circuit (default). 1: disables switchover deglitch circuit. 3 select refb (manual register m ode) if register 0x 01a[1] = 0, select s reference for pll. 0: select s refa. 1: select s refb. 2 stay on refb stay s on refb after switchover. 0: return s to refa automatically when refa status is good again. 1: stay s on refb after switchover. do not automatically return to refa. 1 use ref_sel pin for ref erence s witchover if register 0x01a[0] = 0 (manual), sets method of pll reference selection. 0: uses register 0x01a[3] (default). 1: uses ref_sel pin. 0 enable automatic r ef s witchover automatic or manual reference switchover. 0: manual reference switchover. 1: automatic reference switchover.
data sheet ad9525 rev. 0 | page 39 of 48 table 36. reserved reg. addr . (hex) bit s bit name description 0x 01b [7:0] reserved reserved . 0: default. all bits should be set to 0. table 37. pll block power -down reg. addr . (hex) bits name description 0x01c 7 n divider ecl 2 cmos power - down turns off the n dividers output clock. this stops the clock to the pfd and the frequency monitors. 0: clock on (default). 1: clock off. 6 n divider power - down n divi der power - down. 0: n divider on (default). 1: n divider off. 5 refb divider ecl 2 cmos power - down this bit stops the clock to the frequency monitors for refb. if this bit is disabled , the automatic reference switchover does not operate. in some c onfigurations , enabling the refb d ivider ecl 2 cmos may increase reference spurs on clock outputs. 0: o n. 1: off (default). 4 refa divider ecl 2 cmos power - down this bit stops the clock to the frequency monitors for refa. if this bit is disabled , the automatic reference switchover does not operate. in some configurations , enabling the refa divider ecl 2 cmos may increase reference spurs on clock outputs. 0: on (default). 1: off. 3 ref b d ivider power - down power s down ref b d ivider . the ref b input receiver is still powered up. 0: ref b d ivider on (default). 1: ref b d ivider off. 2 ref a d ivider power - down power s down ref a d ivider . the refa input receiver is still powered up. 0: ref a d ivider on (default). 1: ref a d ivider off. 1 ref b c hannel power - down power s down ref b c hannel . the refb input receiver is powered down. 0: ref b c hannel on. 1: ref b c hannel off (default). 0 ref a c hannel power - down power s down ref a c hannel . the refa input receiver is powered down. 0: r ef a c hannel on (default). 1: ref a c hannel off.
ad9525 data sheet rev. 0 | page 40 of 48 table 38. pll readback reg. addr . (hex) bit s bit name description 0x 01f [7: 5 ] unused unused 4 selected reference shows the reference used by the pll 0: refa 1: refb 3 status f eed back clock status of the feedback clock , as determined by the selected reference 0: missing 1: present 2 status refb status of reference b clock , as determined by the feedback clock 0: missing 1: present 1 status refa status of ref erence a clock , as determined by the feedback clock 0: missing 1: present 0 d igital lock detect (dld) digital lock detect 0: pll not locked 1: pll locked table 39. lv pecl drivers out0 reg. addr . (hex) bit s bit nam e description 0x0f0 [7:5] dont care dont care 4 power d own channel 0 and channel 1 power s d own channel 0 and channel 1 0: e nabled (default) 1: power -d own 3 dont care dont c are [2:1] out0 l evel bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out0 driver power -d own 0: e nabled (default) 1: power -d own table 40. lv pecl drivers out1 reg. addr . (hex) bit s bit name description 0x0f1 [7:5] dont care dont c are 4 reserved reserved , write 0 3 dont care dont c are [2:1] out1 l evel bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out1 driver power - down 0: e nabled (default) 1: power -d own
data sheet ad9525 rev. 0 | page 41 of 48 table 41. lv pecl drivers out2 reg. addr . (he x) bit s bit name description 0x 0f 2 [7:5] dont care dont c are 4 power d own channel 2 and channel 3 power s d own channel 2 and channel 3 0: enabled (default) 1: power -d own 3 dont care dont care [2:1] out2 l evel bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out2 d river p ow er -d own 0: e nabl ed (default) 1: power - down table 42. lv pecl drivers out3 reg. addr . (hex) bits bit name description 0x 0f3 [7:5] dont care dont care 4 reserved r eserved , write 0 3 dont care dont care [2:1] out3 l evel bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out3 driver p ower -d own 0: enabled (default) 1: power - down table 43. pecl drivers out4 reg. addr . (hex) bits bit name description 0x0f4 [7:5] dont care dont care 4 power d own channel 4 and channel 5 power s d own channel 4 and channel 5 0: enabled (default) 1: power - down 3 dont care dont care [2:1] out4 l evel bit 1 bit 0 v od (m v) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out4 driver p ower -d own 0: enabled (default) 1: power - down
ad9525 data sheet rev. 0 | page 42 of 48 table 44. lv pecl drivers out5 reg. addr . (hex) bits bit name description 0x 0f 5 [7:5] dont care dont c are 4 reserved reserved , write 0 3 dont care dont care [2:1] out5 level bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out5 driver power - down 0: enabled (default) 1: power - down table 45. lv p ecl drivers out6 reg. addr . (hex) bits bit name description 0x0f6 [7:5] dont c are 4 powe r down channel 6 and channel 7 power d own channel 6 and channel 7 0: enabled (default) 1: power - down 3 dont c are [2:1] out6 l evel bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out6 d river power -d own 0: enabled (default) 1: power - down table 46. lv pecl drivers out7 reg. addr . (hex) bits bit name description 0x0f7 [7:5] dont care dont c are 4 r eserved reserved , write 0 3 dont care dont care [2:1] out7 level bit 1 bit 0 v od (mv) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0 out7 driver power -d own 0: enabled (default) 1: power - down
data sheet ad9525 rev. 0 | page 43 of 48 table 47. sync_ou t control reg. addr . (hex) bit s bit name description 0x 0f8 [7:5] dont care d ont c are . 4 sync_out channel power - down power s down sync_out channel . 0: enabled . 1: power - down (default) . 3 sync p olarity polarity lvpecl mode . 0: noninverting (defaul t) . 1: inverting . [2:1] sync_out level bit 1 bit 0 v od (mv) 0 0 1 1 0 1 0 1 400 (default) 600 780 960 0 sync_out driver power - down 0: enabled (default) . 1: powers down lvpecl sync_out driver . 0x0f9 [7:5] dont care dont c are . 4 polarity cmos m ode polarity cmos mode . this bit is also used in conjunction with register 0x0f8[3] when the driver is in cmos mode (register 0x0f9[1] = 1). reg. 0x0f9[4] reg. 0x0f8[3] sync out/sync outb 0 0 1 1 0 1 0 1 noninverting/noninverting inverting/invertin g noninverting/inverting inverting/noninverting [3:2] enable cmos drivers sets the cmos driver output configuration when register 0x0f9[1] = 1. bit 3 bit 2 sync_out sync_out 0 0 1 1 0 1 0 1 tristate on tristate on tristate trist ate on on 1 cmos m ode use cmos m ode i nstead of lvpecl mode for sync_out. 0: lvpecl mode (default). 1: cmos mode. 0 sync o ut r esampling e dge s elect sync_out r e sample edge s elect . selects the m divider output edge used to resample the sync clock. 0: use rising edge of m clock (default). 1: use falling edge of m clock . 0x190 [7:0] sync clock s d ivider 16- bit s ync s divider, bits[7:0] (lsb). cycles o f reference c lock = s divider bits[15:0] + 1. for example, [15:0] = 0 is 1 reference clock cycles, [15:0] = 1 is 2 reference clock cycles [15:0] = 65535 is 65536 reference clock cycles . 0x191 [7:0] sync clock s d ivider 16- bit s ync s divider, bits[15:8] (msb). 0x192 [7:5] dont care dont c are . 4 sync e nable 0: disable sync_out (default) . 1: enable sync_ out . note: self - clearing for single shot sync . [3:2] sync s ource bit 1 bit 0 select ref erence for sync clock 0 0 1 1 0 1 0 1 ref: reference input (default) fb: pll feedback n divider power - down: power down sync power - down: power down sync [1:0] sync m ode bit 1 bit 0 sync mode 0 0 single s hot (default) 0 1 periodic 1 0 pseudor andom 1 1 pseudor andom
ad9525 data sheet rev. 0 | page 44 of 48 table 48. vco, reference, and clk inputs reg. addr . (hex) bits bit name description 0x 1e0 [7:3] dont care dont c ar e . [2:0] m d ivider m d ivider value. bit 2 bit 1 bit 0 divider value 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 table 49. other reg. addr . (hex) bits name description 0x230 [7:5] dont care dont care. 4 dist all power - down power s down all of distribution . p uts all drivers in safe power - down mode . 0 (default) : enabled. 1: p ower - down . 3 clkin power - down power s down clkin, clkin . 0 (default): e nabled. 1: p ower - down . 2 m divider power - down power s down m divider. 0 (default): enabled. 1: p o wer - down . 1 distribution reference power - down power down distribution reference. this bit should be asserted only when the drivers do not need t he safe power - down mode guidelines. 0 (default): enabled. 1: p ower - down . 0 pll power - down power down pll. 0 (default): enabled. 1: p ower - down . 232 [7:1] dont care dont care. 0 io_update this bit must be set to 1 b to transfer the cont ents of the buffer registers into the active registers. this happens on the next sclk rising edge. this bit is self - clearing; that is, it does not have to be set back to 0. 1 (self - clearing): update all active registers to the contents of the buffer re gisters.
data sheet ad9525 rev. 0 | page 45 of 48 applications informa tion frequency planning using the ad9525 the ad9525 is a highly flexible pll. when choosing the pll settings and version of the ad9525 , the following guidelines should be kept in mind. the ad9525 has three frequency dividers: the reference (or r) divider, the feedback (or n) divider, and the m d ivider. when trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the m divider or the n divider, thus allowing a higher phase detector freque ncy and more flexibility in choosing the loop bandwidth. choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to f ine - tune the pll loop bandwidth in either direction. adisimclk is a powerful pll modeling tool that can be downloaded from www.analog.com . it is very accurate in determining the optimal loop filter for a given applica tion. using the ad9525 outputs for adc cloc k applications any high speed adc is extremely sensitive to the quality of the sampling clock of the ad9525 . an adc can b e thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog - to - digital output. clock integrity requirements scale with the analog input frequency and resolution, with higher ana log input frequency applications at 14 - bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock. considering an ideal adc of infinite resolution , where the step size and q uantization error can be ignored, the available snr can be expressed , approxi - mately , by ? ? ? ? ? ? ? ? = j a tf snr 2 1 log20 (db) where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 34 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 100fs t j = 200fs t j = 400fs t j = 1ps t j = 2ps t j = 10ps snr = 20log 1 ?i a t j 100 1 1-035 figure 34 . snr and enob vs. analog input frequency for more information, s ee the an - 756 application note , sampled systems and the effects of clock phase noise and jitter , and the an - 501 application note , aperture uncertainty and adc system performance , at www.analog.com . many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. distributing a single - ended clock on a noisy pcb can result in coupled noise on the sampling clock. differential distri - bution has inherent common - mode rejection that can provide superior clock performance in a noisy environment. the differential lvpecl outputs of the ad9525 enable clock s olutions that maximize converter snr performance. the input requirements of the adc (differential or single - ended, logic level termination) should be considered when selecting the best clocking/converter solution.
ad9525 data sheet rev. 0 | page 46 of 48 lvpecl clock distrib ution the lvpecl outpu ts (because t hey are open emitter) require a dc termination to bias the output transistors. the simplified equivalent circuit in figure 22 shows the lvpecl output stage. in most applications, a lvpecl far - end thevenin termina tion (see figure 35 ) or y - termination (see figure 36 ) is recommended . in both cases, vs of the receiving buffer should match vs_drv ( vs_drv = vdd3) . if it does not match, ac coupling is recommended ( see figure 37). vs_drv lvpecl 50? 50? single-ended (not coupled) v s vs_drv lvpecl 127? 127? 83? 83? 100 1 1-036 figure 35 . dc - coupled 3.3 v lvpecl far - end thevenin termination vs_drv lvpecl z 0 = 50? v s = vs_drv lvpecl 50? 50? 50? z 0 = 50? 100 1 1-037 figure 36 . dc - coupled 3.3 v lvpecl y - termination vs_drv lvpecl 100? differential (coupled) transmission line v s lvpecl 100? 0.1nf 0.1nf 200? 200? 100 1 1-038 figure 37 . ac - co upled lvpecl with parallel transmission line lvpecl y - termination is an elegant termination scheme that uses the fewest components and offers both odd - and even - mode impedance matching. even - mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. its main drawback is that it offers limited flexibility for varying the drive strength of the emitter - follower lvpecl driver. this can be an important consideration when driving long trace lengths but is usu ally not an issue. thevenin - equivalent termination uses a resistor network to p rovide 50 ? termination to a dc voltage that is below v ol of the lvpecl driver. in this case, vs_drv on the ad9525 should equal v s of the receiving buffer. although the resistor combination shown results in a d c bias point of vs_drv ? 2 v, the actual common - mode voltage is vs_drv ? 1.3 v because there is additional current flowing from the ad9525 lvpecl driver through the pull - down resistor. sync_out distribution th e sync_out driver of the ad9525 can be configured as cmos drivers. when selected for use as cmos driver s , each output becomes a pair of cmos outputs, each of which can be individually turned on or off and set a s inverting or noninverting. be sure to note the skew difference of using cmos mode v s. lvpecl mode. when single - ended cmos clocking is used, refer to the guidelines presented in the following paragraphs . point - to - point connections should be designed such that each driver has only one receiver, if possible. connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. series termination at the source is generally req uired to provide transmission line matching and/or to reduce cu rrent transients at the driver. the value of the resistor is dependent on the board design and timing requirements (typically 10 ? to 100 ? is used). cmos outputs are also limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inche s are recommended to preserve signal rise/f all times and signal integrity. cmos cmos 10? 60.4? (1.0 inch) microstrip 100 1 1-039 figure 38 . series termination of cmos output termination at the far end of the pcb trace is a second option. the sync_out cmos output of the ad9525 do es not supply enough current to provide a full voltage swing with a low impedance resistive, far - end termination , as shown in figure 39 . the far - end termination network should match th e pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. cmos cmos 10? 50? 100? 100? v s 100 1 1-040 figure 39 . cmos output with far - end termination because of the limitations of single - ended cmos clocking, consider using differential outputs when driving high speed signals over long traces. the ad9525 offers s ync_out lvpecl outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
data sheet ad9525 rev. 0 | page 47 of 48 outline dimensions 112408-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220- wkkd . 1 0.50 bsc bot t om view top view pin 1 indic at or 7.00 bsc sq 48 13 24 25 36 37 12 exposed pa d pin 1 indic at or 5.20 5.10 sq 5.00 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 40 . 48- lead le ad frame chip scale package [lfcsp_w q] 7 mm 7 mm body, very very thin quad cp - 48 -4 dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad95 25 bcpz ? 40c to +85c 48- lead lead f rame chip scale package (lfcsp_w q) cp-48-4 ad95 25 bcpz -r ee l7 ? 40c to +85c 48- lead lead frame chip scale package (lfcsp_w q) cp-48-4 ad95 25 /pcbz evaluation board , no vco ad9525/pcbz- vco evaluation board , 2950 mhz vco installed 1 z = rohs compliant part.
ad9525 data sheet rev. 0 | page 48 of 48 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10011 -0- 10/12(0)

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